ABSTRACT
Nowadays, shifts in Hardware and Software technologies have forced designers and users to look at micro-architecture that process instructions stream with high performance and low power consumption.
In Striving for such high performance, the Queue Processor has been designed with architecture which has the following features:
· Low power consumption
· Smaller code size
· Simple Hardware
· High Performance in terms of Speed
· High Instruction level parallelism
This research aims at comparing and evaluating these performance features of the Queue Processor architecture with the traditionally used RISC architecture. Evaluation will be done in terms of Software (code size, execution time) and Hardware (Logical Elements, power and speed). This evaluation is performed using Quartus II IDE by Altera.
The QSoC will be used as case study for the Queue Processor while Aquarius will be used as case study for the RISC processor.
I’m confident that this evaluation research will show a significant improvement in the performance of the Queue Processor over the RISC Architecture.
TABLE OF CONTENTS
CHAPTER 1 - INTRODUCTION
1.1 Importance of Performance Evaluation
1.2 Research Objectives
1.3 Motivation of Research
1.4 Queue Computing
1.5 Thesis Outline
CHAPTER 2 –LITERATURE REVIEW
2.1 A Short History of Processor Architecture
2.2 Measuring Processor Performance
2.3 Conventional Processor
2.3.1 Issues with Conventional Processors
2.3.2 Architectural Techniques
2.4 Produced Order Queue Computing
2.5 Queue Core Architecture
2.5.1 ALU (Arithmetic Logic Unit)
2.5.2 MLT (Multiplier, Divider and MOD Instructions)
2.5.3 LOAD/STORE
2.5.4 SET
2.5.5 Branch
2.6 Instruction Pipeline Structure
CHAPTER 3 – QUEUE Vs RISC MACHINES
3.1 Queue Machine Analysis
3.1.1 Higher Instruction Level Parallelism (ILP)
3.1.2 Reduced Instruction Width
3.1.3 Free from False Dependencies
3.1.3.1 Register Renaming
3.1.4 Drawbacks of Queue Machines
3.2 QSoC Simulation and Synthesis
3.3 Quartus II Overview
3.4 FPGA Implementation of QSoC
3.5 Pictorial Summary of Queue Machines Vs RISC Machines
CHAPTER 4 – COMPLEXITY ANALYSIS
4.1 Code Size
4.2 Synthesis Result (Logical Elements)
4.3 Power and Speed Comparison Results
CHAPTER 5 - DICUSSION OF RESULTS
CHAPTER 6 - CONCLUSION
6.1 Future Work
REFERENCES
APPENDICES
CHAPTER ONE
INTRODUCTION
1.1 Importance of Performance Evaluation
Performance evaluation is at the foundation of computer architecture research and development. Contemporary microprocessors are so complex that architects cannot design systems based on intuition and simple models only.
Adequate performance evaluation methods are absolutely crucial to steer the research and development process in the right direction. However, rigorous performance evaluation is non-trivial as there are multiple aspects to performance evaluation, such as picking workloads, selecting an appropriate modelling or simulation approach, running the model and interpreting the results using meaningful metrics. Each of these aspects is equally important and a performance evaluation method that lacks rigor in any of these crucial aspects may lead to inaccurate performance data and may drive research and development in a wrong direction [04].
The major aims of Performance Evaluation are to:
· Collect and disseminate information relative to performance aspects, and in particular to a specific topic.
· Promote interdisciplinary flow of technical information among researchers and professionals.
· Serve as a publication medium for various special interest groups in the performance community at large.
1.2 Research Objectives
This research studies extensively, the Queue Processor Architecture in general and evaluates the QSoC (Queue System on Chip) in specific.
This research compares two different processor architectures: Queue Processor (using QSoC from ASL as case study) and RISC Processor (using Aquarius from OpenCores as case study)......
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Item Type: Postgraduate Material | Attribute: 73 pages | Chapters: 1-5
Format: MS Word | Price: N3,000 | Delivery: Within 2hrs
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